1. Field of the Invention
The present invention relates to a flip chip type semiconductor device having a semiconductor chip mounted on its multilayer wiring board and a method of manufacturing the same. In particular, the present invention relates to a flip chip type semiconductor device and a method of manufacturing the same, that is low in manufacturing cost and capable of reducing the wiring pattern pitch of the multilayer wiring board to 10 xcexcm or less.
2. Description of the Related Art
FIGS. 1A and 1B are side views showing a conventional flip chip type semiconductor device 101. The flip chip type semiconductor device 101 shown in FIG. 1A has a semiconductor chip 102, on the peripheral region or active region of which external terminals (not shown) are formed in an area array. Bumps 103 of metal material such as solder, Au, or an Snxe2x80x94Ag alloy are formed as protruded from the external terminals.
As shown in FIG. 1B, the flip chip type semiconductor device 101 is mounted on a multilayer wiring mounting board 104. The multilayer wiring mounting board 104 has electrode pads (not shown) that are formed in the same pattern as the arrangement pattern of the bumps on the flip chip type semiconductor device 101. The flip chip type semiconductor device 101 is mounted on the multilayer wiring mounting board 104 by end users with the bumps 103 in alignment with the electrode pads. When the bumps are made of solder, the flip chip type semiconductor device 101 is typically mounted on the multilayer wiring mounting board 104 by an IR reflow process using flux.
The conventional flip chip type semiconductor device 101, however, has the problem that after the mounting on the multilayer wiring mounting board 104, it deteriorates in mounting reliability, or temperature cycle characteristics in particular, due to a mismatch in the coefficient of linear expansion between the multilayer wiring mounting board 104 and the flip chip type semiconductor device 101. To solve this problem, the following measures have been taken heretofore.
First, it has been attempted to bring the coefficient of linear expansion of the multilayer wiring mounting board 104 close to that of silicon. For example, as disclosed in Japanese Patent Laid-Open Publication No. 2000-323620, ceramic type materials such as AlN, mullite, and glass ceramic, which are expensive, are used to minimize the mismatch in the coefficient of linear expansion for the sake of improved mounting reliability. This attempt is effective in terms of improvement in mounting reliability, whereas the use of the expensive ceramic type materials for the multilayer wiring board usually limits the applications to high-end super computers, large scale computers, and the like.
On the contrary, as disclosed in Japanese Patent Laid-Open Publication No. 2001-203237, for example, there has recently been proposed a technology capable of improving the mounting reliability in which a flip chip type semiconductor device is packaged with an underfill resin interposed between a multilayer wiring board made of inexpensive organic material having a high coefficient of linear expansion and a semiconductor chip. When an underfill resin is thus arranged between the semiconductor chip and the multilayer wiring board made of organic material, shearing stress acting on the bump connecting portions lying between the semiconductor chip and the multilayer wiring board made of organic material can be dispersed for improved mounting reliability. The interposition of the underfill resin between the semiconductor chip and the organic-material multilayer wiring board thus allows the use of the multilayer wiring board that is made of inexpensive organic material.
This conventional art, however, has the problem that the interface between the underfill resin and the semiconductorchip and the interface between the underfill resin and the organic-material multilayer wiring board might suffer delamination and the product might be judged to be defective in a moisture absorption reflow test if the underfill resin contains voids or if the interfaces are poor in adhesive properties. It is therefore impossible for this conventional art to promote a cost reduction of the flip chip type semiconductor device with reliability.
In consideration of the minimum pitch in a bump arrangement pattern and the pin counts, a multilayer wiring board so-called build-up board is typically used as the organic-material multilayer wiring board of the flip chip type semiconductor device. Hereinafter, the method of manufacturing a build-up board will be described with reference to FIGS. 2A through 3C. FIGS. 2A through 2C are sectional views of a conventional build-up board, showing the method of manufacturing the same in the order of steps. FIGS. 3A through 3C are sectional views showing the steps subsequent to that of FIG. 2C.
In FIG. 2A, a Cu foil layer 111 having a predetermined thickness such as 10 to 40 xcexcm is initially pasted on both sides of a core substrate 110 of insulative glass epoxy material, followed by patterning. A hole is drilled in the core substrate 110 before through-hole plating is applied to the interior of the hole, thereby forming a through hole part 112. As a result, the Cu foil layers 111 on both sides of the core substrate 110 are electrically connected with each other. Here, in view of the process stability in the subsequent steps and the quality stability of the substrate, the through hole part 112 is typically filled with an insulative through hole filling resin 113.
As shown in FIG. 2B, an insulative resin 114 is applied to the Cu wiring patterns lying on both sides of the core substrate 110. Insulative resin openings 115 are formed in predetermined positions by photoresist-based chemical etching or a laser machining technique.
As shown in FIG. 2C, metal thin film layers 116 are formed by sputtering metal such as Ti and Cu or through Cu electroless plating, in order that electric connection shall be secured between feed layers intended for Cu electroplating and Cu wiring pattern parts on the core substrate.
As shown in FIG. 3A, photoresists 117 or dry films having a thickness of 20 to 40 xcexcm are arranged on the metal thin film layers 116 and then subjected to exposure and development for the sake of wiring pattern formation through Cu electroplating.
As shown in FIG. 3B, wiring pattern parts 118 are formed by Cu electroplating with the metal thin film layers 116 as the feed layers.
As shown in FIG. 3C, the photoresists 117 or dry films are removed. Using the wiring pattern parts 118 as a mask, the metal thin film layers 116 are then removed by wet etching, so that the wiring pattern parts 118 are electrically independent of each other.
Subsequently, the steps of FIGS. 2B to 3C can be repeated to form a multilayer wiring board having a six- or eight-layer metal structure if needed.
Considering a relaxation of stress resulting from a mismatch in the coefficient of thermal expansion with the core substrate and reliabilities of the multilayer wiring board such as that of the connection via portions, however, the foregoing method of manufacturing a build-up board requires that the photoresists 117 or dry films have a thickness of around 20 to 40 xcexcm to secure the thickness of the build-up layer wiring pattern portions. Thus, in terms of pattern formability at the exposure and development steps, a minimum pitch of 30 xcexcm or so can only be achieved at best. This results in a wiring pattern pitch no smaller than 30 xcexcm or so, which precludes higher densities of the multilayer wiring board and smaller outside dimensions of the board. In typical manufacturing processes, build-up boards are fabricated together on a large panel of approximately 500 mmxc3x97600 mm, and then cut into individual pieces of multilayer wiring boards in the final step. The number of pieces producible per panel can thus be increased if each multilayer wiring board is successfully reduced in outer dimensions. In the current method of manufacturing a build-up board, however, the wiring pattern pitch mentioned above can only be reduced to 30 xcexcm or so at best. It is thus impossible to reduce the outside dimensions of each single multilayer wiring board and to lower the cost of the multilayer wiring board significantly.
The method of manufacturing a multilayer wiring board also has a problem of warpage. The core substrate 110 has a warp, which causes a misalignment of resist patterns in the exposure and development steps for forming the build-up wiring patterns. Such a misalignment leads to a drop in manufacturing yield.
To suppress the warpage of the core substrate, build-up layers must be formed on both sides of the core substrate. It is therefore necessary to form a build-up wiring layer that is essentially needless. As a result, the organic multilayer wiring board must have excessive layers with a drop in manufacturing yield, which is the contributing factor to hinder a reduction in manufacturing cost.
It is an object of the present invention to provide a flip chip type semiconductor device and a method of manufacturing the same in which a multilayer wiring board having a wiring pattern pitch as fine as 10 xcexcm or less can be manufactured at high yield and low cost, no excessive layer is required, and thin films having advantageous electric properties are provided.
A method of manufacturing a flip chip type semiconductor device according to a first aspect of the present invention includes the steps of: forming multilayer thin film wirings on both front and back surfaces of a base substrate having body parts made of metal or an alloy at both the front and back surfaces, each of the multilayer thin film wirings including an inner electrode pad formed on a surface of the multilayer thin film wiring close to the base substrate and an outer electrode pad formed on an opposite surface not close to the base substrate; splitting the base substrate into the front surface side and the back surface side to form two base substrate integrated type wiring boards; removing at least part of the body parts of the base substrates to expose the electrode pad; and mounting a plurality of flip chip type semiconductor chips on the inner electrode pad of the multilayer thin film wiring so that bump electrodes thereof are connected with the inner electrode pad.
In the present invention, the multilayer thin film wirings are formed on the base substrate made of metal or an alloy. Hence, the multilayer thin film wirings improve in flatness. It is therefore possible to form a multilayer wiring board having a wiring pattern pitch as fine as 10 xcexcm or less. After the multilayer thin film wirings are formed on both front and back surfaces of the base substrate, the base substrate is spilt into the front surface side and the back surface side, to form two base substrate integrated type wiring boards. This eliminates the need for forming multilayer wiring layers that are intended to suppress substrate warpage. Since the multilayer thin film wirings formed can be used efficiently and the multilayer thin film wirings can be formed on both the front and back surfaces of the base substrate in a single process, the flip chip type semiconductor device can be manufactured at high yield and low cost.
In the method of manufacturing a flip chip type semiconductor device, according to a second aspect of the invention, solder balls are joined to the outer electrode pad of the multilayer thin film wiring.
According to a third aspect of the invention, the multilayer thin film wiring is separated by each of the semiconductor chips.
According to a fourth aspect of the invention, the step of exposing the inner electrode pad includes the steps of: applying a photoresist to surfaces of the base substrates so as not to cover regions consistent with the electrode pad; and etching off the base substrates with the photoresist as a mask, thereby forming stiffener integrated type multilayer thin film wiring boards having the remaining portions of the base substrates as stiffener parts.
According to a fifth aspect of the invention, in the step of exposing the inner electrode pad, the base substrates are entirely removed to obtain multilayer thin film wirings in film form exposing the inner electrode pad, and after the step, stiffener parts are joined to at least part of the surface of the multilayer thin film wiring from which the base substrates are removed, excluding regions consistent with the inner electrode pad.
According to a sixth aspect of the invention, the stiffener parts are made of metal or an alloy.
According to a seventh aspect of the invention, a resin is filled into between the semiconductor chips and the stiffener parts and between the semiconductor chips and the multilayer thin film wiring after the semiconductor chips are mounted.
According to an eighth aspect of the invention, a heat spreader for cooling the semiconductor chip is joined to each of the semiconductor chips.
According to a ninth aspect of the invention, the inner electrode pad of the multilayer thin film wiring are plated layers formed by electroplating with the base substrate as a feed layer.
According to a tenth aspect of the invention, the base substrate is made of copper, a copper alloy, or stainless steel.
According to an eleventh aspect of the invention, the base substrate is separated into two base substrate integrated type wiring boards by being cut practically in parallel with its surface.
According to a twelfth aspect of the invention, the base substrate has a three-layer structure including metal or alloy body parts on both front and back surfaces and an intermediate metal layer laminated therebetween; and in the step of splitting the base substrate, the intermediate metal layer is etched more selectively than the body parts to separate the base substrate into two.
According to a thirteenth aspect of the invention, a porous film is laminated on the intermediate metal layer.
According to a fourteenth aspect of the invention, the base substrate has a five-layer structure including metal or alloy body parts on both front and back surfaces and a three-layer film arranged therebetween, the three-layer film having two intermediate metal layers and a porous film sandwiched therebetween.
According to a fifteenth aspect of the invention, the base substrate is prepared by stacking two single-layer metal plates made of metal or an alloy, and fixing the single-layer metal plates to each other with a metal or alloy pin sticking therethrough.
According to a sixteenth aspect of the invention, the base substrate is prepared by stacking two single-layer metal plates made of metal or an alloy, and fixing the single-layer metal plates to each other by local welding.
According to a seventeenth aspect of the invention, the base substrate is prepared by stacking two single-layer metal plates made of metal or an alloy, and fixing the single-layer metal plates to each other by mechanical binding at their edges.
According to an eighteenth aspect of the invention, the base substrate is prepared by stacking two single-layer metal plates made of metal or an alloy, and fixing the single-layer metal plates to each other by local bonding with an adhesive.
A flip chip type semiconductor device according to a nineteenth aspect of the invention includes: multilayer thin film wirings including an inner electrode pad formed on one side thereof and an outer electrode pad formed on the other; and a flip chip type semiconductor chips mounted on the multilayer thin film wiring so that a bump electrode thereof is connected with the inner electrode pad of the multilayer thin film wiring, the multilayer thin film wirings being formed by forming the multilayer thin film wirings on both front and back surfaces of a base substrate having body parts made of metal or an alloy at both the front and back surfaces, each of the multilayer thin film wiring including an inner electrode pad formed on a surface of the multilayer thin film wiring closer to the base substrate and an outer electrode pad formed on an opposite surface not close to the base substrate, and then splitting the base substrate into the front surface side and the back surface side, and removing at least part of the body parts of the base substrates to expose the inner electrode pad.
In the flip chip type semiconductor device, according to a twentieth aspect of the invention, the multilayer thin film wiring is separated by semiconductor chip after the semiconductor chip is mounted thereon.
According to a twenty-first aspect of the invention, a stiffener part is made of the base substrate remaining in a region of the multilayer thin film wiring where the semiconductor chip is not mounted on. An insulative sealing resin is arranged between the semiconductor chip and the stiffener part and between the semiconductor chip and the multilayer thin film wiring.
According to a twenty-second aspect of the invention, solder balls are joined to the outer electrode pad of the multilayer thin film wiring.
According to a twenty-third aspect of the invention, a heat spreader for cooling is joined to the semiconductor chip.
According to a twenty-fourth aspect of the invention, the heat spreader is made of a material selected from the group consisting of metallic materials including Cu, Al, W, Mo, Fe, Ni, and Cr, and ceramic materials including alumina, AlN, SiC, and mullite.
According to a twenty-fifth aspect of the invention, the heat spreader is joined to the semiconductor chip with a heat conductive adhesive including, as a main component, a resin selected from the group consisting of epoxy resins, silicone resins, polyimide resins, polyolefin resins, cyanate ester resins, phenol resins, and naphthalene resins, and further including a material selected from the group consisting of Ag, Pd, Cu, Al, Au, Mo, W, diamond, alumina, AlN, mullite, BN, and SiC.
According to a twenty-sixth aspect of the invention, the multilayer thin film wiring is a wiring layer having a multilayer structure formed by forming and patterning an insulative resin thin film and forming and pattering a conductive thin film.
According to a twenty-seventh aspect of the invention, the insulative resin thin film includes, as a main component, a resin selected from the group consisting of epoxy resins, silicone resins, polyimide resins, polyolefin resins, cyanate ester resins, phenol resins, and naphthalene resins.
According to a twenty-eighth aspect of the invention, the multilayer thin film wiring has a metal two-layer structure including: the inner electrode pad; an insulative resin thin film formed to cover the inner electrode pad, having an opening in part of a region consistent with the inner electrode pad; the outer electrode pad formed on the insulative resin thin film and connected to the inner electrode pad through the opening; and a solder resist film for covering an end of the outer electrode pad. According to a twenty-ninth aspect of the invention, the multilayer thin film wiring has a total thickness of 52 to 266 xcexcm.
According to a thirtieth aspect of the invention, the multilayer thin film wiring has a metal three-layer structure including the inner electrode pad, a first insulative resin thin film, a wiring part, a second insulative resin thin film, the outer electrode pad, and the solder resist film. According to a thirty-first aspect of the invention, the multilayer thin film wiring has a total thickness of 77 to 396 xcexcm.
According to a thirty-second aspect of the invention, the multilayer thin film wiring has a metal four-layer structure including the inner electrode pad, a first insulative resin thin film, a first wiring part, a second insulative resin thin film, a second wiring part, a third insulative resin thin film, the outer electrode pad, and the solder resist film. According to a thirty-third aspect of the invention, the multilayer thin film wiring has a total thickness of 102 to 526 xcexcm.
According to a thirty-fourth aspect of the invention, the multilayer thin film wiring has a metal five-layer structure including the inner electrode pad, a first insulative resin thin film, a first wiring part, a second insulative resin thin film, a second wiring part, a third insulative resin thin film, a third wiring part, a fourth insulative resin thin film, the outer electrode pad, and the solder resist film. According to a thirty-fifth aspect of the invention, the multilayer thin film wiring has a total thickness of 127 to 656 xcexcm.
According to a thirty-sixth aspect of the invention, the multilayer thin film wiring has a metal six-layer structure including the inner electrode pad, a first insulative resin thin film, a first wiring part, a second insulative resin thin film, a second wiring part, a third insulative resin thin film, a third wiring part, a fourth insulative resin thin film, a fourth wiring part, a fifth insulative resin thin film, the outer electrode pad, and the solder resist film. According to a thirty-seventh aspect of the invention, the multilayer thin film wiring has a total thickness of 152 to 786 xcexcm.
As described above, according to the present invention, the multilayer thin film wirings are formed on the base substrate that has high flatness. It is therefore possible to form fine wiring which can maintain the high flatness, shows excellent thermal stability during the formation of the multilayer thin film wiring, has high manufacturing yield, and is 10 xcexcm or less in line and space. If the base substrate has a large warp as heretofore, the depth of focus of pattern exposure tends to vary, contributing to manufacturing processes poor in stability. This means technical limitations in terms of fine pattern formability and in view of a drastic improvement in manufacturing cost.
In the present invention, the multilayer thin film wiring can be formed on both front and back surfaces of the base substrate and semiconductor chips can be mounted thereon before the base substrate is split in two to produce two semiconductor devices out of the two surfaces of the base substrate. Then, the production per a single manufacturing process becomes double to allow a significant improvement in manufacturing efficiency with the result of a large reduction in manufacturing cost.
In the method of forming a wiring pattern of the multilayer wiring board according to the present invention, the metal thin film wiring need not necessarily be thickened to around 10-30 xcexcm as with build-up boards in the conventional art. Moreover, it is possible to utilize a method and a system for metalizing a semiconductor wafer. The photoresist and the metal thin film wiring parts can thus be easily processed in a thinner range of 1 xcexcm and below, which facilitates making the wiring patterns finer. With the facilitation of finer wiring patterns, it becomes possible to increase the density of the organic multilayer wiring boards and reduce the outside dimensions of each single multilayer wiring board for a significant reduction in cost. The application of a metal plate(s) to the base substrate significantly reduces the production of waste that matters in conventional printed-wiring boards. This is extremely advantageous in improving manufacturing yield.
Furthermore, when a wafer-shaped base substrate is used, a plurality of packages can be fabricated by wafer-level processes. As compared to packaging methods in which each package is fabricated from a piece, the manufacturing steps can thus be reduced significantly with a large reduction in cost.